As compared to a conventional buck converter, a multi-level buck converter such as a three-level buck converter has several advantages such as increased efficiency at high load states. In addition, the additional switches in multi-level buck converters in combination with the flying capacitor voltage being one-half the input voltage lower the switching stresses as compared to conventional buck converters. Moreover, the ripple is reduced as the four switches in three-level buck converters produce twice the ripple frequency as compared to the ripple frequency at the same switching speed for a conventional (single-phase) buck converter such that the switching frequency is effectively doubled for a three-level buck converter. This increase in output ripple frequency advantageously enables a multi-level buck converter to use a smaller inductor as compared to a conventional buck converter.
As compared to a conventional buck converter, the root-mean-square (RMS) switching node voltage VSW at the input node to the inductor is reduced by 50%. In particular, it can be shown that VSW will switch between the input voltage VIN and one-half of the input voltage if the output voltage is greater than one-half of the input voltage. Conversely, VSW will switch between VIN/2 and ground if VIN/2 is greater than VOUT. This reduction in the switch node voltage swing also reduces the switching voltage stresses on the switching transistors. Given the reduced voltage stress, multi-level buck converters also offer reduced conduction losses for its switch transistors.
But these advantages come at the cost of increased regulation complexity with regard to controlling the multi-level switches. In general, there are four switching states for a four-switch multi-level buck converter as shown in FIG. 1. In each switching state, only two switch transistors are on from a set of four switch transistors: a switch transistor A, a switch transistor B, a switch transistor C, and a switch transistor D. In a switching state D1, switch transistors A and C are on such that the flying capacitor voltage VCF is charged by the input voltage and drives the switch node voltage VSW at the input of the inductor. The resulting inductor current ISW charges an output capacitor with the output voltage VOUT. In a switching state DV, switch transistors C and D are on such that the inductor freewheels and discharges into the output capacitor. The flying capacitor floats during switching state DV. In a switching state D2, switch transistors D and B are on such that the flying capacitor discharges into the switch node. Finally, switch transistors A and B are on in a switching state DP such that the switch node is charged to the input voltage VIN. The flying capacitor floats during switching state DP.
Despite this increased control complexity, prior-art multi-level buck converters have typically employed conventional buck converter control techniques such as valley-mode or peak-mode (peak-current) control. But the transition between valley-mode and peak-mode control in a multi-level buck converter creates a number of control stability issues that are not present in standard buck converters. In particular, note that a transition from peak to valley-mode control is typically unnecessary in a conventional buck converter over a wide range of operating conditions. But conventional multi-level buck converters that use current-mode control to maintain an amps-seconds balance on the flying capacitor transition between valley-mode and peak-current control when the duty cycle ranges from less than 50% to greater than 50% (the duty cycle being defined as the ratio of the output voltage to the input voltage). It is thus conventional to limit multi-level buck converter control to just one of the valley-mode and peak-current control modes. But such a control limitation in turn limits the duty cycle range.
A multi-level buck converter that seamlessly controls the output voltage regardless of the duty cycle is disclosed in commonly-assigned U.S. Pat. No. 9,929,653 (the '653 patent). The multi-level buck converter of the '653 patent selects between the D1, D2, DV, and DP switching depending upon the relationship between an error signal and a dual-ramp signal formed by two ramp signals that are 180 degrees out of phase with each other. If the error signal equals the mid-point of the dual-ramp signal, the switching states D1 and D2 alternate with a 50% duty cycle. But as the error signal rises above the midpoint for the dual-ramp signal, the alternating D1 and D2 switching states are separated by the DP switching state. In particular, the duty cycle for the DP state increases from zero as the error signal increases from the midpoint for the dual-ramp signal. Conversely, the DV states separates the alternating D1 and D2 switching states as the error signal falls below the midpoint such that the duty cycle for the DV state increases from zero as the error signal decreases from the midpoint for the dual-ramp signal.
The resulting control solves the limitation of prior art multi-level buck converters being dedicated to a particular duty cycle range. However, note that there is a minimum pulse width for the DV and DP switching states. But as the error signal transitions to be just slightly greater or less than the midpoint for the dual-ramp signals, the desired pulse width for the DV or DP switching states may be less than the minimum pulse width (which may also be designated as a minimum pulse duration). The control algorithm may call for a pulse width for the DV or DP switching states that is some fraction of the minimum pulse width as the error signal transitions from being equaling the midpoint for the dual-ramp signal. But this desired fractional pulse width cannot be achieved. Although the control algorithm commands for a DV or DP pulse width of some fractional amount, what can be achieved is instead the minimum pulse width. This difference between the desired duration for the DV and DP switching states and the minimum duration that can be implemented results in undesirable magnetization or demagnetization of the inductor current. Accordingly, there is a need in the art for an improved multi-level buck converter employing dual-ramp signal control having a minimum pulse width for the switching states that achieves the desired magnetization or demagnetization of the inductor current as the error signal transitions from equaling the midpoint for the dual-ramp signal.
The multi-level buck converter disclosed in the '653 patent also regulates the flying capacitor voltage by adjusting the D1 and D2 pulse widths. But this regulation of the flying capacitor voltage raises another issue for dual-ramp control architectures which is that the current though the multi-level transistor switches cannot exceed a current limit to prevent damage to the multi-level transistor switches and also to increase safety of the device. Thus, the control algorithm may command for a certain pulse width or duration for the D1 and D2 switching states that cannot be achieved due to the current limit being reached. As a result, the flying capacitor voltage may fall out of regulation due to the inability to achieve the desired D1 and D2 pulse widths. Accordingly, there is a need in the art for an improved multi-level buck converter employing dual-ramp signal control in the presence of over-current conditions.